Current initialization procedures for DDR links generally suffer from a “chicken-and-egg” problem in that a pattern is written to memory and then read back from the memory. However, the writing process may be in error, which provides an incorrect result for a read operation. Because the error may be the result of a write operation or a read operation, an iterative and often relatively time consuming initiation process is often used, with algorithms needing sophistication and larger volume of data to isolate the cause of the errors. This results in system inefficiencies and extended training times.
FIG. 1 is a flow diagram of conventional initialization of a DDR link. In response to a reset condition, 100, a self-calibration process is initiated, 110. Command, Control and Clock signal timing is determined, 120. Write leveling operations are performed, 130. Read leveling operations are performed, 140.
Read training, 150, and write training, 160, are performed. The read and write training is an iterative process in which values are written to memory and read from memory to determine whether the read and write operations are error-free. Errors may occur, for example, from cross-talk cause by line bundling and/or interleaving of signal lines. The iterative read and write training is the result of the chicken-and-egg condition discussed above. Upon completion of the read and write training, post-training read and write operations may be performed, 170.